1. Technical Field
The present disclosure relates to the manufacturing of integrated circuits. The present disclosure relates more particularly to controlling the different processes which are applied to the semiconductor wafers during the manufacturing of integrated circuits, and particularly the lithography, etching, polishing and planarization processes. The present disclosure also relates to the validation of the masks used during the lithography processing.
2. Description of the Related Art
A lithography process classically comprises steps of depositing a resist layer made of light-sensitive resin onto a wafer made of a semi-conductive material, and of exposing the resist layer through a mask, to radiation (visible light, ultraviolet light, X rays, beam of electrons, etc.). The resist layer exposed to the radiation is then developed so as to form a mask on the wafer. The wafer and the mask formed in the resist layer may then be subjected to an etching process. The mask formed by the resist layer on the wafer may also be used particularly for wet stripping or implants to be performed.
However, these different processes, and in particular the lithography, have limits in terms of miniaturization of integrated circuits. Indeed, the smaller the shapes to be produced on a wafer are, the greater the differences between the shapes desired and the shapes produced are, particularly due to the diffraction effects produced by the mask on the exposure radiation of the mask.
To reduce these differences and in particular the effects of the diffraction during the exposure of a semiconductor wafer through a mask, a technique referred to as Optical Proximity Correction (OPC) has been developed. This technique includes modifying the mask by taking into account the effects of optical proximity so as obtain patterns having a shape as similar as possible to the desired shape. FIG. 1 schematically represents steps of a method PRS1 for generating corrected masks. The method comprises a step TPG of extracting test structures to form a test pattern TP from data defining a mask layout LO. The test structures are basic shapes corresponding to shapes of the layout LO which are critical, i.e. sensitive to the diffraction phenomenon. A test pattern commonly comprises hundreds, or even thousands of basic structures to be representative of the critical shapes to be produced. During a next step MW, the layout LO and test pattern TP data are used to produce a lithography mask MSK. A lithography process LITP through the mask MSK is then applied to a semiconductor wafer W previously covered with a resist layer. During a next step MSD, critical dimensions are measured on the test pattern TP transferred to the wafer W, and possibly on shapes of the layout LO. These measurements are compared with the dimensions of the corresponding shapes on the mask MSK or specified by the layout data LO to obtain Edge Placement Error (EPE) measurements of the critical shapes. The EPE measurements obtained in step MSD are used to determine corrections to be applied to the structures of the layout LO and generate in step OPC a corrected layout CLO, including possibly a corrected test pattern. The layout CLO is then used to generate a new mask (step MW). The new mask is then used to process a new wafer W (step LITP). Measurements are taken on the new wafer to determine the EPE errors (step MSD). If the errors measured are below a certain threshold, the last mask MSK generated is considered valid, otherwise the steps OPC, MW, LITP and MSD are performed again until the EPE errors are below the threshold.
In certain cases, it may be desired to change the layout LO. The method steps described previously must then be executed again.
A Model-Based Optical Proximity Correction (MBOPC) technique has also been developed to determine the aperture threshold of the resist layer according to the shape of a curve of radiation intensity on the resist layer through the mask, it being possible to calculate the curve of radiation intensity on the resist layer for any pattern structure printed on the mask. Thus, the MBOPC technique enables an aperture threshold for the resist layer to be predicted according to variations in the intensity of the radiation applied to the resist layer through a mask. The variations in radiation intensity applied to the resist layer through the mask can be calculated for any pattern configuration. The MBOPC technique also enables the modifications to be made to the geometric features of the patterns to be deduced to obtain structures on a semiconductor wafer which have shapes as similar as possible to a desired layout.
A model is generally defined in accordance with the method PRS2 represented in FIG. 2. The method PRS2 differs from the method PRS1 in that it comprises a modeling step MDLG using a modeling software program enabling EPE measurements to be processed to extract therefrom an aperture threshold model for the resist layer MDL. The aperture threshold of the resist layer corresponds to the radiation intensity necessary to entirely pierce the resist layer. The mask MSK is then corrected using the model MDL to form structures on the wafer W that are similar to the desired layout LO. If the EPE measurements obtained with the new mask are satisfactory, the model is used by the mask production software program to generate other masks having the same integration level. If, on the contrary, the error measurements are too significant, the steps MDLG, OPC, MW, LITP and MSD are executed again until a model is obtained enabling a satisfactory corrected mask to be produced.
An OPC-type model generally comprises an optical model and a processing model. The optical theory at the origin of the optical model is perfectly known and the corresponding calculations can be done accurately (H. H. Hopkins, “The Concept of Partial Coherence in Optics”, In Proc. Royal Soc. Series A., Vol. 217, p. 408, 1953, and “On the Diffraction Theory of Optical Images”, In Proc. Royal Soc. Series A., Vol. 217, No. 1131, p. 408-432, 1953). The settings of the lithography tools are used to create an optical model which can be adapted to correspond to the empirical data. Software available in the market has been designed for performing approximate calculations of radiation intensity using a breakdown into eigenvectors of the function used to calculate a so-called “aerial” image of the radiation intensities applied to the resist layer through a mask. These calculations relate to millions of structures in the form of a polygon on an actual mask, and are not therefore possible in an industrial environment. Therefore, the OPC-type model performs approximations taking into account only the most “energetic” eigenvectors. However, the generation of a mask takes into account the influence of these approximations on the accuracy obtained.
A processing model is primarily empirical. The radiation intensity variations are simulated thanks to the optical model at points located on line segments referred to as “sites” passing through edges of the structures to be produced on a semiconductor wafer. The combination of this simulation with measurements made using a Scanning Electron Microscope (SEM) on the semiconductor wafer on numerous structures enables a polynomial interpolation to be performed which is supposed to predict for each site located on a structure, the position of the aperture threshold of the resist layer, on the basis of an aerial image simulation.
A processing model MDL therefore classically comprises a polynomial enabling an approximate value of the aperture threshold to be calculated according to shape parameters relating to the curve of radiation intensity on the resist layer through the mask, in the vicinity of a structure edge. The intensity curve shape parameters which are determined empirically, may particularly comprise maximum and minimum local intensities, a maximum slope of the intensity curve (derived from the first order of the curve), the intensity at the point at which the slope of the curve is maximum, the curvature (derived from the second order) of the curve at the point at which the slope of the curve is maximum, the empirical and theoretical aperture thresholds of the resist layer, and the theoretical and empirical values of the Edge Placement Error (EPE) of the pattern. The polynomial used to calculate the aperture threshold of the resist layer is for example as follows:thr=−0.74862+3.13872 SL−1.95222 SL2+0.23562 IX−0.65241 IX2+0.40022 IX3−0.05458 CRV+0.00577 CRV2  (1)wherein SL is the maximum slope, IX the maximum value and CRV the curvature of the intensity curve at the point at which the slope is maximum.
A model may generally be validated by a so-called “sparse” simulation. The sparse simulation uses the model MDL to calculate the so-called “aerial” light intensity, i.e. on the resist layer at points located on line segments referred to as “sites” passing through edges of shapes to be produced on a semiconductor wafer.
Thus, in FIG. 2, the method PRS2 comprises a simulation step SIM enabling simulation of edge placement error (SEPE) measurements to be obtained from the model MDL and from the test pattern TP and/or from the layout LO. Therefore, a model MDL particularly enables the effects of displacing segments in terms of edge placement error to be predicted, without having to print a mask and transfer the mask onto a semiconductor wafer.
During first modeling steps, a model is extracted from a mask layout and validated by applying a lithography and etching process to a semiconductor wafer using a mask, and by performing validation measurements on the processed wafer using images of the wafer obtained for example using a Scanning Electron Microscope (SEM). It will be understood that other systems capable of reaching resolutions similar to that of an SEM can be used, such as an Atomic-Force Microscope (AFM), a Scanning-Tunneling Microscope (STM), or a Transmission Electron Microscope (TEM).
FIG. 3 represents an example of structure the contour of which has the shape of a polygon M1. FIG. 3 also shows the sites SS where measurements are taken. The sites SS are positioned on the polygon M1 by the user during the constitution of the model. During the constitution of the model, each polygon M1 is divided using a fragmentation algorithm which cuts the polygon forming the pattern into segments, with one segment per site SS. The segments of the polygon M1 are delimited in FIG. 3 by the points PF. FIG. 3 also shows, superposed on the structure M1, a structure M2 as simulated or formed on a wafer W from the structure M1. It can be seen that all the angles of the structure M1 have disappeared in the structure M2 particularly due to the effects of the diffraction. The model resulting from the EPE measurements depends on the chosen site positions.
FIG. 4 represents a light intensity curve I(x) representative of the light intensity applied to the resist layer, along a site SS, x being the distance in nm between the point considered and the edge of the structure. In FIG. 4, the curve C1 is between maximum IX and minimum IN intensity values and has a maximum slope SL. The point of aperture of the resist layer (x=0) is within a zone in which the curve C1 reaches the maximum slope SL.
FIG. 5 represents a structure M1′ derived from the structure M1, after correction OPC. The derived structure M1′ has been obtained by shifting outwards the segments (for example sg1) corresponding to recessed zones (compared to the structure M1) in the produced corresponding structure M2, and by shifting towards the interior of the structure M1, the segments (for example sg2) corresponding to excess zones (compared to the structure M1) in the structure M2.
So-called “dense” 2D simulation methods have also been developed. Dense simulations are performed directly on images obtained for example using a Scanning Electron Microscope (SEM), by comparing the polygonal contours simulated with those extracted from the images. Dense simulations enable better accuracy and exhaustiveness to be achieved, but need greater computing powers and times. To reduce the extent of the calculations to be done, provision can be made to apply a dense simulation only to the test pattern TP. Generally, the choice between a sparse simulation and a dense simulation depends on the complexity and on the level of accuracy of the layout. Due to its cost, the dense simulation is used only when it is very important, particularly when the accuracy of the structures to be formed on a semiconductor wafer reaches 45 nm or is below this value.
As explained above, the structures corrected using the model are validated by printing them on a mask, then by transferring them onto a semiconductor wafer, and finally by performing measurements on the wafer. This validation which involves hundreds of measuring points is extremely time consuming, particularly in terms of computing time, and a high level of skill is needed to use the data obtained. The result of these disadvantages is that it is impossible to control all the structures of a mask and to control the wafers in a production line in real time. There are indeed very few conventional ways of controlling wafers being processed, after a lithography exposure and/or an etching process. One of these ways includes performing on each critical masking level a few SEM measurements of critical structures on isolated measurement sites, or in broader zones, or by using a scatterometer on zones that are consistent in size. This solution is not totally reliable, insofar as it does not enable all the defects likely to appear on the wafers being produced to be detected. Indeed, it is not possible to perform systematic measurements in zones in which the light intensity has an unfavorable shape.
Furthermore, numerous parameters determine the conditions in which the processes are applied to a semiconductor wafer. These parameters particularly determine the lighting conditions, and in particular the light intensity applied to the mask, the focus of the light on the resist layer, the thickness of the resist layer and the conditions of applying the etching process. It transpires that these parameters may fluctuate particularly according to ambient conditions and even cause manufacturing defects of the integrated circuits on the wafer. In the absence of exhaustive monitoring of the manufacturing of integrated circuits, it is not therefore possible to guarantee accuracy and quality in the manufacturing lines of high quantities.
It is therefore desirable to be able to monitor in real time a production line to detect drifts in the settings of the manufacturing parameters and particularly the lithography and etching phases.
Furthermore, it may be desired to change the manufacturing settings or to slightly alter a mask. Such changes cause hundreds of structures to be measured again using an SEM. Each validation step involves many hours of SEM utilization, even if the measurements are automated. These measurements also cause substantial analysis work to be done by a highly qualified person. Then several steps of processing a wafer are implemented. For this purpose, it is thus common to use large quantities of semiconductor wafers to perform exploration tests. As the rapid inspection of all the tests is not possible, one makes choices before the OPC validation, with the risk of eventually finding out that the model is not compatible with the manufacturing process at the time of the final verification.